Nvidia's Jensen Huang introduced the layer cake framing to describe AI's economic architecture from the ground up. It is simple, correct, and underappreciated by investors who focus exclusively on the application layer. Each layer has distinct market size, margin characteristics, competitive structure, and investment duration. Reading from bottom to top:

The US electrical grid was designed around a world of relatively predictable, geographically dispersed demand growth. AI data centres are the opposite: sudden, enormous, geographically concentrated loads appearing in areas whose grid was sized for agricultural or light industrial use. The mismatch between what hyperscalers need and what the grid can deliver is the primary real-world constraint on AI infrastructure buildout — not chip supply, not permitting for data centre construction, but transformer availability and transmission capacity.

The numbers are stark. A single large EHV (Extra High Voltage) transformer — the type required to step down transmission-level power for a hyperscale campus — costs $3–7M, weighs 200–400 tonnes, and has a lead time of 18–24 months from order to delivery. There are only a handful of manufacturers globally capable of producing them at the required voltage class: ABB, Siemens Energy, Hitachi Energy, SPX Transformer Solutions in the US. Combined global production capacity is estimated at 700–900 units per year against rising demand. The supply of transformers has become one of the least-discussed but most practically constraining bottlenecks in the AI infrastructure buildout.

In the prior generation of data centre buildout, site selection was driven by fibre connectivity, real estate cost, and tax incentives. For AI-era hyperscale campuses, the dominant variable has shifted to available power and grid headroom. Virginia — historically the world's largest data centre market — is facing a power availability crisis: Dominion Energy has effectively paused new large-load interconnection approvals in parts of Northern Virginia due to transmission constraints. This has redirected investment to new geographies: the Pacific Northwest (hydro-abundant), Texas (ERCOT grid flexibility), the upper Midwest (cheap wind + available transmission), and internationally, the Nordic countries (hydro + cold climate) and the Middle East (sovereign capital + land + willingness to build dedicated generation).

The implication for the investment thesis is that geographic power availability is becoming a durable competitive advantage for data centre operators who secured land and power agreements early. Equinix and Digital Realty — the dominant colocation REITs — have decades of site relationships that are difficult to replicate. Hyperscalers building their own campuses are racing to secure long-term power purchase agreements before available capacity is fully contracted.

Understanding the stack architecturally is one thing. Understanding where durable economics accumulate is another. The history of technology platform buildouts — railways, telephony, the internet — suggests that infrastructure layers produce durable returns for the components where switching costs are highest and replication is hardest, while applications and services above the platform compete away margins unless they develop independent network effects or data advantages. AI is following an analogous pattern.

Three structural questions determine where value accrues in any technology value chain: Who is irreplaceable? Who benefits from rising volume without proportional cost? And who controls the bottleneck that constrains everyone else? Mapping the AI hardware stack against these questions produces a clear hierarchy.

A semiconductor chip is one of the most complex manufactured objects in human history — a product requiring the coordinated output of dozens of specialist industries, across multiple geographies, under tolerances measured in atoms. The value chain that produces it is not a linear assembly line but an intricate lattice of interdependent specialisations, each representing decades of accumulated knowledge that cannot be transferred quickly or cheaply.

Understanding the structure of this value chain — who does what, where the margin sits, and where the chokepoints are — is prerequisite to understanding why certain companies are structurally irreplaceable. It also explains why the geopolitical contest over semiconductor supply chains has become the central economic and strategic conflict of the 2020s.

The semiconductor industry organises itself along a fundamental structural choice: whether to design chips, fabricate chips, or both. This choice — made once and expensive to reverse — shapes everything about a company's economics, risk profile, and competitive position.

The most consequential product decision in AI hardware is the choice of compute architecture. Training and running AI models requires processing enormous volumes of matrix multiplication — an operation that different chip architectures handle with very different efficiency, cost, and flexibility trade-offs. The dominant architecture today is the GPU. The challengers are custom ASICs. And the incumbent general-purpose CPU is now largely irrelevant for AI accelerator workloads at scale.

Nvidia's dominance in AI is not primarily a hardware story. It is a software story. CUDA — NVIDIA's parallel computing platform launched in 2006 — is the reason. When AI researchers began experimenting with GPU training in the early 2010s, they did so on CUDA. Every framework (TensorFlow, PyTorch), every library (cuDNN, cuBLAS), every optimised model was built for and tested on CUDA-enabled hardware. By the time AI demand exploded in 2023, the software ecosystem lock-in was so deep that switching away from Nvidia was not a hardware decision — it was a software, tooling, and retraining decision affecting every ML engineer in the world.

This is the key insight that gets lost in the GPU vs ASIC debate: Nvidia's moat is CUDA, not the H100. The H100 will be superseded by the H200, B100, B200, and whatever comes next. But the CUDA ecosystem — 4 million+ developers, 3,500+ GPU-accelerated applications, 15+ years of optimisation — is extremely hard to displace regardless of hardware competition.

The custom silicon programs at Google (TPU v5), Amazon (Trainium 2, Inferentia 3), Microsoft (Maia 100), and Meta (MTIA) represent the most credible threat to Nvidia's market share. The economics are compelling at hyperscaler scale: a custom chip designed specifically for your inference workload can deliver 20–40% better performance-per-watt, which at a million-chip deployment translates into hundreds of millions of dollars annually in energy savings and foregone Nvidia procurement spend.

But the threat is structurally bounded. Custom ASICs require: (1) sufficient volume to justify $500M+ design investment; (2) workload stability — the chip must be designed for a workflow that will not change before the chip ships; (3) internal silicon engineering teams of 500–1,000+ engineers (rare outside the Big 4 hyperscalers); and (4) 2–4 years of lead time from design to production. These requirements confine viable ASIC programs to a handful of the world's most resource-endowed companies. The long tail of AI companies — thousands of enterprises, startups, and research institutions — will buy Nvidia for the foreseeable future.

TSMC is the most consequential company that most investors outside the technology sector have never deeply analysed. It fabricates approximately 90% of the world's most advanced semiconductors. It is the reason Nvidia's H100 exists, the reason Apple's M-series chips are competitive, and the reason the US government has spent $52 billion via the CHIPS Act trying to build domestic alternatives. Understanding why TSMC's moat exists — and why it is so hard to replicate — requires engaging with physics, economics, and organisational knowledge simultaneously.

TSMC's primary fabs are in Taiwan — a geopolitical fact that has become the semiconductor industry's most discussed and least resolved risk. Approximately 92% of the world's leading-edge (sub-5nm) chip production capacity is located in Taiwan as of 2024. The US CHIPS Act, Japan's semiconductor subsidies, and the EU Chips Act are all attempts to redistribute this concentration — but the pace of geographic diversification is structurally constrained by the same factors that created the concentration in the first place.

Memory is the least glamorous part of the semiconductor value chain — and, since 2023, the most important bottleneck in the AI hardware stack. The reason is simple: AI inference and training are not compute-bound at the frequencies that matter; they are memory-bandwidth-bound. The limiting factor in running a large language model is not the speed at which the GPU performs matrix multiplications — it is the speed at which it can feed data to itself from memory. This is why HBM (High Bandwidth Memory) became the critical component, and why SK Hynix — the company that delivers it at volume — became arguably as important to the AI supply chain as TSMC.

The reason HBM became scarce — and why SK Hynix captured a disproportionate share of AI memory value — is a story about a technology bet made years before the AI boom. In 2018–2020, SK Hynix made a strategic decision to invest heavily in HBM3 development, betting that the convergence of GPU compute and memory-intensive ML workloads would create demand that standard DRAM could not serve. Samsung, the larger company, hedged more conservatively. Micron focused on standard DRAM and NAND cycles.

When Nvidia began designing the H100 in 2020–2021, TSMC and Nvidia turned to SK Hynix as the only supplier with both the HBM3 technology and the production ramp capability at the necessary scale. By the time the H100 launched in 2022 and AI demand exploded in 2023, SK Hynix was effectively the sole-source supplier for the critical memory component of the world's most sought-after chip. The resulting pricing power — HBM3E sells at 5–8x the price of equivalent-capacity standard DRAM — has driven SK Hynix's DRAM gross margins to levels not seen in a decade.

The semiconductor industry has always been globally interdependent — chips designed in California, fabricated in Taiwan, assembled in Malaysia, sold worldwide. That interdependence is now the central theatre of the US-China strategic competition. Since 2019, the US has progressively restricted China's access to advanced semiconductors and the tools to make them. The restrictions have escalated with each administration, producing a supply chain fragmentation that is reshaping where chips are made, who can buy them, and what the long-run cost structure of the industry looks like.

The geopolitics section in v1 of this document documented what happened chronologically but did not commit to an analytical view on what it means. That is an evasion. The US-China chip restrictions produce two materially different futures with genuinely different investment implications, and a serious framework should be explicit about which is more probable and what the second-order effects of each are.

One structural shift that the chip architecture analysis in Section 05 raised but did not fully resolve: the workload mix is shifting from training to inference, and this shift has different implications for the competitive landscape than a simple "more AI = more Nvidia" extrapolation.

Training workloads are large, parallelisable, and batch-processed. They run for days or weeks on clusters of thousands of GPUs. Flexibility across model architectures matters because researchers iterate frequently. This is Nvidia's home turf — CUDA + H100/B100 is optimised for exactly this workload.

Inference workloads are different in character: they require low latency (milliseconds, not minutes), high throughput at lower batch sizes, and relentless cost-per-token optimisation. A frontier LLM serving 2.5 billion queries per day is an inference problem, not a training problem. The optimal chip architecture for inference prioritises energy efficiency and memory bandwidth utilisation over raw floating-point performance. This is where the architecture competition opens up:

The v1 document mentioned hyperscaler custom ASICs as a competitive threat to Nvidia. The fuller picture is more structural: hyperscalers are not just building chips — they are vertically integrating across the entire stack in a way that progressively reduces their dependence on third-party vendors at every layer.

Google designs its own TPUs, runs them in its own data centres, on its own grid-connected power infrastructure, serving its own model (Gemini) through its own cloud platform. The only external dependencies are TSMC (fabrication) and ASML (via TSMC). Amazon has Trainium chips, Graviton CPUs, its own DC construction capability, AWS Outposts for edge, and long-term nuclear PPAs. Microsoft has Maia ASICs, Azure infrastructure, and the Constellation Energy nuclear PPA. Meta has MTIA inference chips, its own massive DC build programme, and is the largest single customer for Nvidia — while simultaneously building the alternative.

This vertical integration dynamic is not a short-term threat to chip layer economics — the volumes required and the complexity of the transition mean hyperscalers will remain large Nvidia customers for years. But it is the structural force that will gradually compress Nvidia's pricing power at the hyperscaler segment and push Nvidia's growth increasingly toward the enterprise/cloud-customer segment where CUDA lock-in is strongest and custom silicon economics are least compelling.

Across the sections of this study, a clear hierarchy of competitive positioning has emerged. The moat scores below reflect structural durability (not near-term earnings), assessed across switching cost, replication difficulty, and time to catch up.

A rigorous investment framework must ask not just what makes the thesis work but what would cause it to fail entirely. The AI hardware thesis — own the physical constraint, compound with the moat — rests on a set of assumptions that are well-grounded in current evidence but are not immutable laws. The following are the scenarios that would materially break the thesis rather than merely slow it down. They are assigned low probability but deserve explicit framing because their consequences are high enough to warrant position sizing that accounts for them.